? 2007 device engineering incorporated page 1 of 8 ds-mw-01026-01 rev.b not recommended for new design ? use DEI1026a 08/13/07 12k 12k 12k 12k 12k 12k + - + - 2k 2k + - 2k + - 2k + - 2k + - 2k 3.1v reference gnd out 1 out 2 out 3 out 4 out 5 out 6 in 1 in 2 in 3 in 4 in 5 in 6 v dd ce oe 12k 2k vdd DEI1026 six channel discrete-to-digital interface sensing open/ground signals device engineering incorporated 385 east alamo drive chandler, az 85225 phone: (480) 303-0822 fax: (480) 303-0824 e-mail: admin @ deiaz.com features: ? senses six open/ground inputs ? inputs are lightning protected to do-160d level 3 ? ttl/cmos-compatible tri-state outputs ? package / temperature options: ? 16 lead .150? soic, -55 c /+85 c ? 16 lead ceramic 300mil sop, -55 c /+125 c soic package option shown functional description: the DEI1026 is a six channel discrete-to-digital interface bicmos device. it senses six open/ground discrete signals of the type commonly found in avionic systems. the inverted 3-state outputs are ttl/cmos compatible and are enabled by the oe and ce pins. the inputs are lightning protected to meet the requirements of do160d sec 22 waveforms 3, 4, and 5, level 3. see figures 5-7. the device is available in a 16 lead .150 soic and .300 ceramic sop. with its reliability, low cost, operating range, and lightning protection, the DEI1026 meets a large variety of interface requirements for aerospace applications. figure 1: function diagram figure 2: pinout diagram 7 6 5 4 3 2 1 10 11 12 13 14 15 16 in 1 9 8 v dd in 2 in 3 in 4 in 5 in 6 oe ce out 6 out 5 out 4 out 3 out 2 out 1 gnd
? 2007 device engineering incorporated page 2 of 8 ds-mw-01026-01 rev.b not recommended for new design ? use DEI1026a 08/13/07 table 1: absolute maximum ratings parameter min max units supply voltage v dd -0.3 7.0 v discrete input voltage (pins 1-6) -5 +40 * v digital input voltage (ce and oe) v ss - 0.3 v dd + 0.3 v lightning protection (pins 1-6) do160d, waveform 3; level 3 do160d, waveforms 4, and 5; level 3 -600 -300 +600 +300 v junction temperature 145 o c storage temperature plastic ceramic -55 -55 150 150 o c operating free air temperature plastic ceramic -55 -55 85 125 o c the DEI1026 contains circuitry to protect inputs from dama ge due to electrostatic discharge. it has been characterized per jedec a114-a human body model to class 1. observe pr ecautions for handling and storing electrostatic sensitive devices. * the DEI1026 will withstand the transi ent surge dc voltage step function loci limits for category b equipment per mil- std-704a. table 2: DEI1026 device operating characteristics parameter symbol conditions min typ max units supply voltage v dd 4.5 5.0 5.5 v free air operating temp. t a v dd = 4.5 ? 5.5 v plastic ceramic -55 -55 85 125 o c logic output sink current i ol v dd = 4.5 ? 5.5 v 5.0 ma logic output source current i oh v dd = 4.5 ? 5.5 v -5.0 ma table 3: DEI1026 logic truth table ce (chip enable) oe (output enable) discrete input output 0 0 open 0 0 0 ground 1 1 x x high z x 1 x high z
? 2007 device engineering incorporated page 3 of 8 ds-mw-01026-01 rev.b not recommended for new design ? use DEI1026a 08/13/07 table 4a: DEI1026-ses (plastic) electrical ch aracteristics (t a = -55 c to +85 c , v dd = 4.5 to 5.5 v, unless otherwise noted) parameter symbol conditions min typ max units power supply characteristics supply current i dd v in = v dd (all inputs) v dd = 5.5 v 5 10 ma discrete input characteristics ground state input voltage v sg voltage source from input terminal to ground for logic high output. 3.0 v open state input voltage v so voltage source from input terminal to ground for logic low output. 3.5 v ground state input resistor r ig resistor from input to ground to guarantee logic high output. 0 100 ? open state input resistor r io resistor from input to ground to guarantee logic low output. 100k ? input source current i io current sourced into 100 ohm resistor to ground. -100 -330 a reverse leakage current i ir v in = 35 v, v dd = 0 v 100 a logic input characteristics ce, oe input logic 1 level v ih 2.0 v ce, oe input logic 0 level v il 0.8 v dc output characteristics output logic 1 level (ttl) v oh i oh = -5 ma 2.4 v output logic 0 level (ttl) v ol i ol = 5 ma (2) 0.4 v output logic 1 level (cmos) v oh i oh = -100 a v dd ? 50mv v output logic 0 level (cmos) v ol i ol = 100 a v ss + 50mv v off-state output current i oz oe = v dd v dd = 5.5 v v out = 0 or v dd +/-10 a switching characteristics [1] i/o propagation delay t hl , t lh refer to figure 4. 150 ns delay from ce or oe input (with output low) to output hi-z t lz refer to figure 3. 25 ns delay from ce or oe input (with output hi-z) to output low t zl refer to figure 3. 25 ns delay from ce or oe input (with output high) to output hi -z t hz refer to figure 3. 25 ns delay from ce or oe input (with output hi-z) to output high t zh refer to figure 3. 25 ns
? 2007 device engineering incorporated page 4 of 8 ds-mw-01026-01 rev.b not recommended for new design ? use DEI1026a 08/13/07 table 4b: DEI1026-wm[ ] (ceram ic) electrical characteristics (t a = -55 c to +125 c , v dd = 4.5 to 5.5 v, unless otherwise noted) parameter symbol conditions min typ max units power supply characteristics supply current i dd v in = v dd (all inputs) v dd = 5.5 v 5 10 ma discrete input characteristics ground state input voltage v sg voltage source from input terminal to ground for logic high output. 3.0 v open state input voltage v so voltage source from input terminal to ground for logic low output. 3.5 v ground state input resistor r ig resistor from input to ground to guarantee logic high output. 0 100 ? open state input resistor r io resistor from input to ground to guarantee logic low output. 100k ? input source current i io current sourced into 100 ohm resistor to ground. -100 -330 a reverse leakage current i ir v in = 35 v, v dd = 0 v 100 a logic input characteristics ce, oe input logic 1 level v ih 2.0 v ce, oe input logic 0 level v il 0.8 v dc output characteristics output logic 1 level (ttl) v oh i oh = -5 ma 2.4 v output logic 0 level (ttl) v ol i ol = 5 ma (2) 0.4 v output logic 1 level (cmos) v oh i oh = -100 a v dd ? 50mv v output logic 0 level (cmos) v ol i ol = 100 a v ss + 50mv v off-state output current i oz o e = v dd v dd = 5.5 v v out = 0 or v dd +/-10 a switching characteristics [1] i/o propagation delay t hl , t lh refer to figure 4. 170 ns delay from ce or oe input (with output low) to output hi-z t lz refer to figure 3. 30 ns delay from ce or oe input (with output hi-z) to output low t zl refer to figure 3. 30 ns delay from ce or oe input (with output high) to output hi -z t hz refer to figure 3. 30 ns delay from ce or oe input (with output hi-z) to output high t zh refer to figure 3. 30 ns notes: 1. guaranteed by design and not production tested. 2. limit the sum of all iol currents to 20ma. th e vsg spec may exceed limit beyond this current.
? 2007 device engineering incorporated page 5 of 8 ds-mw-01026-01 rev.b not recommended for new design ? use DEI1026a 08/13/07
? 2007 device engineering incorporated page 6 of 8 ds-mw-01026-01 rev.b not recommended for new design ? use DEI1026a 08/13/07 table 5: package characteristics package type 16 lead soic narrow body 16 lead soic narrow body, green 16 lead ceramic sop reference 16l soic nb 16l soic nb g 16l csop thermal resistance: ja (4 layer pcb with power planes) 74 c/w 74 c/w - jc 24 c/w 24 c/w 23 c/w jedec moisture sensitivity level (msl) msl 2 / 235 c msl 2 / 260 c hermetic lead finish material / jedec pb-free code snpb nipdau e4 au e4 pb-free designation not pb-free rohs compliant pb free jedec reference ms-012-ac ms-012-ac -
? 2007 device engineering incorporated page 7 of 8 ds-mw-01026-01 rev.b not recommended for new design ? use DEI1026a 08/13/07 figure 8: mechanical outline, 16 lead 0.150? soic figure 9: mechanical outline, 16 lead ceramic sop
? 2007 device engineering incorporated page 8 of 8 ds-mw-01026-01 rev.b not recommended for new design ? use DEI1026a 08/13/07 table 6: ordering information dei part number marking (1) package op. temp. range processing DEI1026 DEI1026 16l soic nb -55 / +85oc standard DEI1026-g DEI1026 e4 (2) 16l soic nb g -55 / +85oc standard DEI1026-wms DEI1026-wms 16 lead ceramic sop -55 / +125oc standard DEI1026-wmb DEI1026-wmb 16 lead ceramic sop -55 / +125oc burn in, 96 hr @125oc notes: 1. all packages marked with lot code and date code. 2. ?e4? after date code denotes pb free category. dei reserves the right to make changes to an y products or specifications herein. dei makes no warranty, representation, or gua rantee regarding suitability of its pro ducts for any particular purpose.
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